1. Field of the Invention
The present invention relates to the field of boundary scan interfaces in accordance with the IEEE 1149.1 standard developed by the Joint Test Action Group (JTAG), and more specifically to the equipment used in connection with circuits employing these boundary scans (hereinafter JTAG) interfaces.
2. Description of the Related Art
Electrically programmable logic devices (EPLDs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs) are well known in the art. These devices can be programmed by integrated circuit designers to implement particular logic functions. To program an EPLD, CPLD, or FPGA, the device is typically connected to a computer system via an interface cable and the computer system is instructed to download program information into the device. The EPLD, CPLD, or FPGA (hereinafter the programmable logic device or PLD) retains this programming information in nonvolatile computer memory (e.g., flash memory, EEPROM, etc.) or in volatile computer memory (e.g., SRAM).
In the past, the JTAG interface was used primarily for testing devices that were soldered or otherwise fixed to a circuit board. Using the JTAG interface, instructions were sent from a computer system to the mounted devices to test for open circuits and short circuits associated with the pins of those devices. Recently, the JTAG interface has been used to program PLDs that are board mounted (i.e. in-system programmable (ISP) devices). To facilitate this programming, multiple PLDs are coupled in a chain in accordance with the IEEE 1149.1 boundary scan standard. The first device in the JTAG chain, which is coupled to the programming computer via a JTAG interface cable, can be programmed and then put into a bypass mode so that other downstream devices in the JTAG chain are programmed sequentially.
To accomplish this programming, the ISP software includes complex software routines to control the programming order of the PLDs in the JTAG chain. Thus, the programming data is written into the JTAG chain using the placement order of the PLDs. However, the designer often does not have access to the physical embodiment of the JTAG chain that is being programmed, thereby preventing the ISP software from being tested and verified in conjunction with the JTAG chain. Alternatively, the designer has access to the JTAG chain, but wants to test the JTAG chain independently from the overall electronic design.
To solve this problem in the past, the physical JTAG chain was constructed using prototype material, e.g. wirewrap and prototype circuit boards (protoboards). The designer then used the physical JTAG chain to test the ISP software. However, this prototype construction is tedious, complex, and error-prone, thereby making the process disadvantageous for small JTAG chains and entirely impractical for large JTAG chains. Therefore, a need exists for a structure that facilitates testing ISP software and other aspects pertinent to a physical JTAG chain.
Accordingly, the present invention provides a structure that allows any number of PLDs, of any type and in any order, to be coupled together into a physical JTAG chain. Thus, the present invention facilitates the quick and easy construction of custom JTAG chains that can be used for a broad range of diagnostic purposes. One such diagnostic purpose is to test software designed for ISP PLDs that conform to the IEEE 1149.1 boundary scan standard.
In accordance with the present invention, an interface board includes a plurality of JTAG interfaces for receiving one or more modular integrated circuit (IC) interface cards. Each card has a socket of a particular package type for receiving an IC of the same package type and a connector interface, coupled to the socket, for a removable coupling with one of the standard interfaces of the interface board.
The traces of the interface board provide certain JTAG signals, e.g. a test mode select (TMS) signal and a test clock (TCK) signal, to all of the JTAG interfaces (and thus to the modular IC interface cards and ICs in the JTAG chain) in parallel. Other JTAG signals, e.g. a test data input (TDI) signal and a test data output (TDO) signal, are routed through the ICs in series. Specifically, the TDO signal of one IC becomes the TDI signal of the next IC in the chain. The TDO signal of the last IC in the JTAG chain is provided as a test data final (TDF) signal from the interface board back to a cable (which communicates with the programming system). If less than the maximum number of modular IC interface cards are inserted into the interface board, a terminator card is inserted into the JTAG interface following the last modular IC interface card of the JTAG chain. This terminator card provides the TDF signal.
In accordance with one embodiment of the present invention, the interface board further includes an output cascade connector that can be coupled to an input cascade connector of another interface board. The cascade connectors facilitate the transfer of the JTAG signals between the interface boards. In this manner, any number of interface boards can be coupled in series to expand the size of the physical JTAG chain.